--**************************************************************************--

--
-- UART
--

--**************************************************************************--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--**************************************************************************--

entity UART is 
	port(rst : in STD_LOGIC;
	     clk : in STD_LOGIC;
	     uartclk : in STD_LOGIC;
	     memadl : in STD_LOGIC_VECTOR (7 downto 0);
	     memadh : in STD_LOGIC_VECTOR (7 downto 0);
	     upp0 : inout STD_LOGIC_VECTOR (7 downto 0);
	     upwr : in STD_LOGIC;
	     uprd : in STD_LOGIC;
	     trx  : out STD_LOGIC);
end UART;


--**************************************************************************--

architecture BHV of UART is

        constant CZ_8 : STD_LOGIC_VECTOR (7 downto 0) := "ZZZZZZZZ";
        constant C1_8 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";

	-- uart state type
	type STATE_TYPE is (IDLE, START_BIT, STOP_BIT, BIT0, BIT1, BIT2,
			    BIT3, BIT4, BIT5, BIT6, BIT7);

	-- uart data and ack addresses
	constant REGS_ADDRH : STD_LOGIC_VECTOR (7 downto 0) := "11111111"; 
	constant REG1_ADDRL : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
	constant REG2_ADDRL : STD_LOGIC_VECTOR (7 downto 0) := "00000001";

	-- signals for communication between the cpu write and uart transmit process
	signal uart_ack  : STD_LOGIC;
	signal uart_en   : STD_LOGIC;
	signal uart_data : STD_LOGIC_VECTOR(7 downto 0);
	
	-- signals used in the uart transmit process
	signal state : STATE_TYPE;	
begin
	--
	-- cpu read/write
	--
	process(rst, clk)
	begin
		if( rst = '0' ) then
			uart_en <= '0';
			uart_data <= "00000000";
			upp0 <= C1_8;
		elsif( clk'event and clk = '1' ) then
			upp0 <= CZ_8;

			-- ????
						
			if( upwr = '0' ) then
				if( memadh = REGS_ADDRH and memadl = REG1_ADDRL ) then
					-- ????
				end if;
			elsif( uprd = '0' ) then
                                if( memadh = REGS_ADDRH and memadl = REG2_ADDRL ) then
					-- ????
                                end if;
                        end if;
		end if;
	end process;
	
	--
	-- UART serial transmit process
	--
	process(rst, uartclk) 
	begin
		if( rst = '0' ) then
			uart_ack <= '1';
			trx <= '1';
			state <= IDLE;
		elsif( uartclk'event and uartclk = '1' ) then
			case state is
				-- ????
			end case;
		end if;
	end process;
end BHV;