--
-- Roman Lysecky
--

--**************************************************************************--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--**************************************************************************--

entity UARTCLKDIV is 
	port(rst : in STD_LOGIC;
	     clk : in STD_LOGIC;
	     uartclk : out STD_LOGIC);
end UARTCLKDIV;

--**************************************************************************--

architecture UARTCLKDIV_ARCH of UARTCLKDIV is

	-- constants used to reset, increment, and 
	constant C0_24 : UNSIGNED (23 downto 0) := "000000000000000000000000";
	constant C1_24 : UNSIGNED (23 downto 0) := "000000000000000000000001";
	constant CM_24 : UNSIGNED (23 downto 0) := ""; -- determine value to create a clk for 1200 bps UART
		
	signal clkval : STD_LOGIC;
	signal i : UNSIGNED (23 downto 0);
begin
	process(rst, clk)
	begin
		if( rst = '0' ) then
			uartclk <= '0';
			clkval <= '0';
			i <= C0_24;
		elsif( clk'event and clk = '1' ) then
			if( i = CM_24 ) then
				-- add code to toggle uartclk
				i <= C0_24;
			else
				i <= i + C1_24;
			end if;
		end if;
	end process;
	
end UARTCLKDIV_ARCH;