--
-- Tony Givargis
--

--**************************************************************************--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--**************************************************************************--

entity XS40 is 
	port(rst : in STD_LOGIC;
             clk : in STD_LOGIC;
             uprst : out STD_LOGIC;
             upclk : out STD_LOGIC;
	     uppsen : in STD_LOGIC;
	     upale : in STD_LOGIC;
	     uprd : in STD_LOGIC;
	     upwr : in STD_LOGIC;
	     upp0 : inout STD_LOGIC_VECTOR (7 downto 0);
	     memadl : inout STD_LOGIC_VECTOR (7 downto 0);
	     memadh : in STD_LOGIC_VECTOR (7 downto 0);
	     memoe : out STD_LOGIC;
	     memcs : out STD_LOGIC;
	     trx : out STD_LOGIC);
end XS40;

--**************************************************************************--

architecture XS40_ARCH of XS40 is

	component UART
	port(rst : in STD_LOGIC;
	     clk : in STD_LOGIC;
	     uartclk : in STD_LOGIC;
	     memadl : in STD_LOGIC_VECTOR (7 downto 0);
	     memadh : in STD_LOGIC_VECTOR (7 downto 0);
	     upp0 : inout STD_LOGIC_VECTOR (7 downto 0);
	     upwr : in STD_LOGIC;
	     uprd : in STD_LOGIC;
	     trx : out STD_LOGIC);
	end component;

	component CTRUP
		port(rst : in STD_LOGIC;
		     clk : in STD_LOGIC;
		     uprst : out STD_LOGIC;
		     upclk : out STD_LOGIC;
		     uppsen : in STD_LOGIC;
		     upale : in STD_LOGIC;
		     upp0 : in STD_LOGIC_VECTOR (7 downto 0);
		     uprd : in STD_LOGIC;
		     memadl : out STD_LOGIC_VECTOR (7 downto 0);
		     memoe : out STD_LOGIC;
		     memcs : out STD_LOGIC);
	end component;

	component UARTCLKDIV is 
		port(rst : in STD_LOGIC;
		     clk : in STD_LOGIC;
		     uartclk : out STD_LOGIC);
	end component;

	signal uartclk : STD_LOGIC;
begin
	U0 : UARTCLKDIV port map(rst, clk, uartclk);
	U1 : CTRUP port map(rst, clk, uprst, upclk, uppsen, upale, upp0, uprd, memadl, memoe, memcs);
	U2 : UART port map(rst, clk, uartclk, memadl, memadh, upp0, upwr, uprd, trx);		
end XS40_ARCH;