Unfortunately, the term entity has two meanings in the VHDL
literature. First, it is used to signify the complete description for
a component. Second, it used to refer to the VHDL construct in which
a component's interface is described. The appropriate definition,
however, is generally discernible from the context in which the term
is used. In the context of this slide, for example, the student
should use the first of the two definitions above.
No matter what level of abstraction is used for a VHDL model, the
relationship between the model and its outside, as observed through its
interface, must be described. A behavioral description of that
relationship is generally the most abstract where specific details
about a component's internal structure need not be made available, if
in fact, they even exist at this point in the system's design.
Each device in VHDL behaves as a process performing operations
on the input to the device and writes to the output. This input and
output information is carried in constructs called signals
which are the chief means of communication between VHDL entities.
Signals in VHDL are roughly similar to wires in the real world.
