The structure of signal assignment statement allows some flexibility.
However, the signal type of the result on the right hand side must
match the type of the signal being assigned. This is illustrated in
the first two assignments shown on the right.
The third assignment shows the use of a single after clause
used to control how much simulation time must pass before the assigned
signal takes on its new value.
As seen in the fourth example, multiple assignments can be made in a
single statements by separating them with commas. This sequence of
assignments is called a "waveform".
If a signal assignment statement has no after clause, a clause
equivalent to "after 1 delta cycle" is implied. Delta cycles are key
to the VHDL timing model and have been previously discussed in the
VHDL Basics module.
