VHDL Packages
What can you put in a package?
Subprograms
(i.e., functions and procedures)
Data and
type declarations
such as:
User
record
definition
User types and enumerated types
Constants
Files
Aliases
Attributes
Component declarations
Entities and Architectures
cannot
be declared or defined in a package
To use a package, make it visible via the "use" language construct