Although signal assignments may resemble variable
assignments syntactically, VHDL signals serve a different
purpose. Signals are used to pass information directly between
VHDL processes and entities. As has already been
described, signal assignments require a delay before the
signal assumes its new value. In fact, a particular
signal may have a series of future values with their respective
timestamps pending in the signal's waveform. The need to
maintain a waveform results in a VHDL signal requiring
more simulator resources than a VHDL variable.
