VHDL Objects:

Signals vs Variables (cont. 1)

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In this example, variables are used to achieve the same functionality as the example in the previous slide. In this example, however, when there is a change in a at time 1, both out_3 and out_4 will also assume their new values at time 1 because they are variables, and VHDL variable assignment statements result in the new values being assumed immediately.

Also note, however, that in this example, the order in which the statements appear within the process is important because the two statements are executed sequentially, and the process will only be executed once as a result of the single change in a.