Just as with the read and write memory procedures, we check for reset
whenever a wait condition exists in the process.
The process executes a typical processor cycle -- fetch next
instruction, decode the instruction, and execute the instruction. In
this model, decoding is performed by doing type conversion on
slices of the instruction, and execution is performed using a VHDL
case statement.
Not all of the instructions are shown since there are quite a few of
them. But the general pattern can be observed.
For example, the ADD operation is performed simply by making a call to
the add procedure. Note that heavy use of casting is done to
translate variable types passing in and out of procedures.
The load operation is shown here to demonstrate the activities that
must take place. Two memory reads are performed; the first is to obtain the
displacement, and the second is to fetch the desired data.
A branch instruction operates in several steps.
-
Read the displacement from memory
-
Calculate the condition
-
Set the PC accordingly
Note the use of the others clause at the end of the case
statement. Even if all op-code patterns were used in the case
statement (which is not the case here), it is good modeling practice
to always use an others clause to report anomalous modeling
behavior.
