The SDSP Clock Model

Note that the clock period is defined as twice the clock pulse width, Tpw, and a very small separation between clock pulses (to ensure non-overlapping clock phases), Tps. Since these values are constant, we define them as generics.

The clock is generated by setting phi1 and phi2 to '1' or '0' and using after clauses to shift the phase of phi2 relative to phi1. The process executes once each clock period to create the next clock cycle.