The entity statement can include additional information.
In this case, the GENERIC declaration creates a parameter to be passed
to the architectures of this entity. The generic prop_delay is
created with a default value of 10 ns. At component instantiation,
however, prop_delay could be set to any value of type time.
Any object declared in an entity's GENERIC declaration is available as
a read-only object within any architecture of that entity. For
example, an architecture for the entity above may contain a signal
assignment of the form
a <= b after prop_delay;
Generics are discussed further in the 'Structural VHDL' module.
