-- Our first program in VHDL
-- This is how comments look in VHDL

-- Libraries are needed for std_logic type to be understood
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
		  
-- Entity part is a specification of the chip interface
ENTITY test1 is
	PORT (a: IN std_logic;
	      b: IN std_logic;
	      x: OUT std_logic);
END test1;

-- Architecture part (otherwise called: body or implementation)
-- determines the operation of a circuitry being designed
ARCHITECTURE OfMyTest1 OF test1 IS
BEGIN
	PROCESS(a, b)
	BEGIN
		x <= a AND b;
	END PROCESS;
END OfMyTest1;
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