Xilinx x4000 series VHDL Simulation Models

Introduction

This is the second external BETA Release (v1.4) of the Xilinx x4000 series FPGA vhdl models. This release now supports the x4000 and x4000e series Xilinx parts. The x2000, x3000, and the new x4000ex series are not supported.

Methodology

The modeling methodology was divided into two tasks.
  1. Xilinx x4000 model library - create vhdl models for the x4000 series structures. These include buffer, tristate buffer, flip-flop/latch, clb, iob, oscillator, and startup components. Boundary scan is planned to be included at a later date.
  2. lca2vhd - Convert a design's post routed lca file into a vhdl structural design composed of these structures. This structural model includes the extracted routing delays from the lca file as well as the configuration data needed to configure these structures. This is accomplished by a perl script lca2vhd.

About this Release

The BETA 1.4 release is a full functional model (with the exceptions noted) that includes almost all timing information including routed wire delays extracted from the lca file. This BETA version currently performs no timing violation checks (no setup, hold, or pulse width check are performed). These will be added in future releases.

If you should have any questions concerning these models please contact: