BEGIN
-- check for reset active
IF reset = '1' THEN
read <= '0' AFTER Tpd;
write <= '0' AFTER Tpd;
fetch <= '0' AFTER Tpd;
d_bus <= null AFTER Tpd;
PC := X"0000_0000";
WAIT UNTIL reset = '0';
END IF;
-- fetch next instruction
memory_read(PC, true, current_instr);
IF reset/= '1' THEN
add(PC, bits_to_int(PC), 1, temp_V, temp_N, temp_Z);
--decode & execute
op := current_instr(31 DOWNTO 24);
r3 := bits_to_natural(current_instr(23 DOWNTO 16));
r1 := bits_to_natural(current_instr(15 DOWNTO 8));
r2 := bits_to_natural(current_instr(7 DOWNTO 0));
i8 := bits_to_int(current_instr(7 DOWNTO 0)); |
CASE op IS
WHEN op_add =>
add(reg(r3), bits_to_int(reg(r1)), buts_to_int(reg(r2)), cc_V, cc_N, cc_Z);
WHEN op_addq =>
add(reg(r3), bits_to_int(reg(r1)), i8, cc_V, cc_N, cc_Z);
WHEN op_sub =>
subtract(reg(r3), bits_to_int(reg(r1)), bits_to_int(reg(r2)), cc_V, cc_N, cc_Z);
. . . . . . . . .
WHEN op_land =>
reg(r3) := reg(r2);
cc_Z := bool_to_bit(reg(r3) = X"0000_0000");
. . . . . . . . .
WHEN op_ld =>
memory_read(PC, true, displacement);
IF reset /= '1' then add (PC, bits_to_int(PC), 1, temp_V, temp_N, temp_Z);
add(effective_addr, bits_to_int(reg(r1)),
bits_to_int(displacement), temp_V, temp_N, temp_Z);
. . . . . . . . . |
.......
WHEN op_bi => memory_read(PC, true, displacement);
IF reset /= '1' THEN
add(PC, bits_to_int(PC), 1, temp_V, temp_N, temp_Z);
add(effective_addr, bits_to_int(reg(r1)), bits_to_int(displacement),
temp_V, temp_N, temp_Z);
IF ((cm_V and cc_V) OR (cm_N and cc_N) OR (cm_Z and cc_Z)) = cm_i
THEN
PC := effective_addr;
END IF;
END IF;
WHEN op_brq =>
add(effective_addr, bits_to_int(PC, i8, temp_V, temp_n, temp_Z);
if ((cm_V and cc_V) or (cm_N and cc_N) or (cm_Z and cc_Z)) = cm_i
THEN
PC := effective_adr;
END IF;
.........
WHEN OTHERS => ASSERT false REPORT "illegal instruction" SEVERITY WARNING;
end case;
end if; -- reset /= '1'
end process;
end behavior; |
